1. Field of the Invention
Embodiments of the present invention relate to a method of forming a chip carrier substrate to alleviate chip cracking, and a chip carrier formed thereby.
2. Description of the Related Art
The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are becoming widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, PDAs and cellular telephones.
While a wide variety of packaging configurations are known, flash memory storage cards may in general be fabricated as system-in-a-package (SiP) or multichip modules (MCM), where a plurality of dice are mounted on a substrate. The substrate may in general include a rigid base having a conductive layer etched on one or both sides. Electrical connections are formed between the dice and the conductive layer(s), and the conductive layer(s) provide an electric lead structure for integration of the dice into an electronic system. Once electrical connections between the dice and substrate are made, the assembly is then typically encased in a molding compound to provide a protective package.
In view of the small form factor requirements, as well as the fact that flash memory cards need to be removable and not permanently attached to a printed circuit board, such cards are often built of a land grid array (LGA) package. In an LGA package, the semiconductor dice is electrically connected to exposed contact fingers formed on a lower surface of the package. External electrical connection with other electronic components on a host printed circuit board is accomplished by bringing the contact fingers into pressure contact with complementary electrical pads on the printed circuit board. LGA packages are ideal for flash memory cards in that they have a smaller profile and lower inductance than pin grid array (PGA) and ball grid array (BGA) packages.
A cross-section of a conventional LGA package is shown in FIG. 1. One or more die 20 are mounted on a substrate 22 via die attach 24. The substrate 22 in general is formed of a rigid core 26, of for example polyimide laminate. Thin film copper layers 28 may be formed on the core in a desired electrical lead pattern, including exposed surfaces for the contact fingers, using known photolithography and etching processes. The contact fingers 30 may be formed of a layer of gold deposited on the copper layer 28 to provide the electrical connection of the package to the host PCB. The dice may be electrically connected to the substrate by wire bonds 32. Vias (not shown) are formed through the substrate to allow electrical connection of the dice through the substrate to the contact fingers 30. The substrate may then be coated with a solder mask 34, leaving the contact fingers 30 exposed, to insulate and protect the electrical lead pattern form on the substrate. Further examples of typical LGA packages are disclosed in U.S. Pat. Nos. 4,684,184, 5,199,889 and 5,232,372, which patents are incorporated by reference herein in their entirety.
Referring now to FIG. 2, after the dice is mounted onto the substrate, the assembly is packaged within a molding compound 40 to protect the assembly. During the molding process, the molding machine may output an injection force typically about 0.8 tons to drive the molding compound into the mold cavity. For dice having a footprint of about 4.5 mm by 2.5 mm, this injection force may result in a pressure down on the dice of about 1.2 kgf/mm2.
The bottom surface of an LGA package is typically not flat. As shown in FIGS. 1 and 2, the fingers 30 are recessed within the package, above the plane defined by the solder mask 34. The flush position of the solder mask results in an equal and opposite force pushing upward on the substrate, against the force of the mold compound, at positions beneath the lower surface solder mask. However, as the contact fingers are not flush with the lower surface of the solder mask, there is no equal and opposite force at positions beneath the contact fingers. This results in stress buildup within the dice at positions in the dice located over the contact fingers.
In the past, semiconductor die were better able to withstand the stress generated during the molding process in LGA packages. However, chip scale packages (CSP) and the constant drive toward smaller form factor packages require very thin dice. It is presently known to employ wafer backgrind during the semiconductor fabrication process to thin dice to a range of about 8 mils to 20 mils. At these thicknesses, the dice are often not able to withstand the stresses generated during the molding process, and the dice deform under the molding pressure (as shown by the dashed lines in FIG. 2).
Deformation of the dice over the contact fingers can cause fractures in the dice, known as die cracking, such as the die crack 50 shown in FIG. 2. Die cracking under the stress of the molding process will generally result in the package having to be discarded. Occurring at the end of the semiconductor fabrication and packaging process, this is an especially costly and burdensome problem.
The problem of die cracking has not previously been addressed by the chip carrier substrates. The area on the top side of the substrate, above the contact fingers on the bottom side of the substrate, generally include layer 28 of copper, etched for example in a mesh pattern as shown in prior art FIG. 3. It is also known to provide a solid uniform layer of copper above the contact fingers as shown in prior art FIG. 4. However, owing to differences in thermal expansion coefficients, a solid uniform layer of copper on the substrates leads to warping and other problems during the elevated temperature processes during package formation. Moreover, with thin semiconductor die, die cracking occurs at unacceptably high rates during the molding process with either one of the patterns shown in FIGS. 3 and 4.